Implementación de un Hardware econfigurable de los Bloques de un Sistema RSA
Field programmable gate arrays Hardware design languages Residue arithmetic Public key cryptography.
Main Article Content
In this work the hardware design of the constituent elements of a RSA system is presented. This document shows the design and simulation results of the four blocks in which the RSA system can be split. Individual performances of such blocks are presented, and the future work on this subject is presented too
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Bolaños Martínez F, Nieto Londoño RD, Bernal Noreña Álvaro. Implementación de un Hardware econfigurable de los Bloques de un Sistema RSA. inycomp [Internet]. 2004 Jun. 7 [cited 2024 Dec. 22];6(2):25-34. Available from: https://revistaingenieria.univalle.edu.co/index.php/ingenieria_y_competitividad/article/view/2276
- Rubén D. Nieto-Londoño, Álvaro Bernal Noreña, Estado del arte en las metodologías de diseño de circuitos digitales asíncronos , Ingeniería y Competitividad: Vol. 7 No. 2 (2005)
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