A methodological approach for asynchronous implementation of the Rijndael Algorithm

Abstract

This  article  describes  the  implementation  methodology  of  Rijndael  algorithm  to  encryption  process,  by  using  asynchronous design with assistance of the software tool Balsa, for functional simulation, description and synthesis of asynchronous digital circuits. The main results presented correspond to implementations that use the codification protocols dual-rail and 1-of-4, for blocks of data and keys of 128 bits over a field-programmable gate array (FPGA) hardware platform. The Xilinx ISE tool was used showing a full integration level with the Balsa system.